1. Field of the Invention
Embodiments of the present invention generally relate to computer-aided design of integrated circuits and, more specifically, to the generation of various models from a common database.
2. Description of the Related Art
Conventional computer-aided design of integrated circuits uses different code databases to generate various models of the integrated circuit. A significant number of man and machine hours are needed to verify that the different models are correct. For example, an architectural model, typically written by an engineering team, of the integrated circuit is used to define the functional requirements. A register transfer level (RTL) model of the integrated circuit is then produced, typically by another engineering team, and the functionality of the RTL model is verified against the architectural model. A cycle accurate performance model of the integrated circuit may also be developed to tune the architectural model and the RTL model. Because each model is developed using a different language, verification of each model is essential to ensure the fabricated integrated circuit functions properly. However, verification of each model is also time consuming, for example, typically requiring writing of verification testbenches and tests and of formal verification testbenches and assertions.
Accordingly, there is a need for a high-level language that may be used to generate a common database from which various models of an integrated circuit can be generated.